In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high carrier mobility structures for CMOS applications. Traditionally, to boast performance of NFET and PFET devices, the prior art method to implement this has been to grow strained Si layers on thick (on the order of from about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for prior art heterostructures; the use of thick SiGe buffer layers has several noticeable disadvantages associated therewith. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations (TDs) and misfit dislocations, are from about 106 to about 108 defects/cm2 which are still too high for realistic VLSI (very large scale integration) applications. Thirdly, the nature of the prior art structure precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In order to produce relaxed SiGe material on a Si substrate, prior art methods typically grow a uniform, graded or stepped, SiGe layer to beyond the metastable critical thickness (i.e., the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations, through the SiGe buffer layer. Various buffer structures have been used in an attempt to increase the length of the misfit dislocation section in the structures and thereby to decrease the TD density.
When a typical prior art metastable strained SiGe layer is annealed at a sufficiently high temperature, misfit dislocations will form and grow thereby relieving the total strain on the film. In other words, the initial elastic strain of the film is relieved by the onset of plastic deformation of the crystal lattice. For the case of prior art metastable strained SiGe grown on SOI substrates, experiments have shown that under most annealing/oxidation conditions, the formation of misfit dislocations occurs early in the annealing history for temperatures greater than ˜700° C. Many of these defects are then either consumed or annihilated during the high-temperature annealing of the structure, however, the surface topography of the original misfit array persists during oxidation. Furthermore, SGOI substrate materials fabricated by thermal diffusion do not completely relax the SiGe alloy layer. Instead, the final SiGe lattice expands only to some fraction of the equilibrium value.
If the Si layer in the initial SOI substrate were truly allowed to “float” with respect to the buried oxide (BOX) layer, then the initial strain in the metastable SiGe/Si bilayer structure could be relieved elastically by sliding along the Si/buried oxide boundary (i.e., elastic relaxation). Although it has been conjectured that this happens naturally at the Si/BOX interface (at a sufficiently high temperature), thorough investigation of this idea has shown that this does not happen (at the macroscopic scale) and misfit arrays form when annealing initially metastable bilayer films.
In view of the problems mentioned with prior art processes of fabricating SGOI substrate materials, there is a continued need for providing a new and improved method that allows for the enhanced low-temperature elastic relaxation of metastable SiGe alloys grown on SOI substrates.